Historically, most performance improvements in semiconductor field-effect transistors (FET) have been achieved by scaling down the relative dimensions of the device. This trend is becoming increasingly more difficult to maintain as the devices reach their physical scaling limits. As a consequence, advanced FETs and the complementary metal oxide semiconductor (CMOS) circuits in which they can be found are increasingly relying on strain engineering and specialty silicon-on-insulator substrates to achieve desired circuit performance. However, the ion implantation steps used in fabricating the FETs relying on these enhancements present two particular challenges.
The first challenge pertains to source/drain (S/D) implants in CMOS fabricated in ultrathin silicon-on-insulator (UTSOI) substrates, where the UTSOI layer is typically in the range from 6 to 30 nm in thickness. It is difficult to implant the desired concentration of certain dopant species in the S/D regions without amorphizing the entire SOI layer. If there is no crystalline Si left under the amorphized S/D regions to act as a seed or template, the S/D recrystallization will be highly defective (and thus unsuitable for high performance devices). Through-SOI-thickness amorphization is of particular concern with heavy ions such as As+ and with UTSOI layers on the thin end of the thickness range. This problem is illustrated in FIG. 1 in which the basic steps of a S/D implant and annealing process for an UTSOI FET having a desired outcome are shown in FIGS. 1A-1C and the basic steps of a S/D implant and annealing process having an undesired outcome are shown in FIGS. 1D-1F.
FIG. 1A shows UTSOI FET 10 at an early stage of processing. UTSOI FET 10 comprises single crystal UTSOI layer 20 disposed on buried oxide (box) layer 30 on base substrate 40, with conductive gate 50 disposed on gate dielectric 60 over UTSOI channel region 70 separating UTSOI S/D regions 80. FIG. 1B shows the structure of FIG. 1A after S/D regions 80 have been amorphized with ion implant 90 to create amorphized S/D regions 100. Residual crystalline regions 80′ remain under amorphized S/D regions, providing a template for the amorphized S/D regions to recrystallize by solid phase epitaxy (SPE) during subsequent activation annealing to produce single-crystal S/D regions 80″, as shown in FIG. 1C.
FIGS. 1D-1F show what happens when the same implant 90 is applied to the slightly thinner UTSOI layer 120 of FIG. 1D. In this case, ion implant 90 produces amorphized S/D regions 130 extending all the way to box layer 30, as shown in FIG. 1E. Due to the lack of a single crystal Si template, recrystallization of these amorphized S/D regions during subsequent activation annealing thus produces polycrystalline S/D regions 140, as shown in FIG. 1F. This is undesirable because doped polycrystalline Si has a much higher resistance than crystalline Si having the same dopant density.
The second challenge pertains to FETs relying on strain engineering. In these FETs, the channel regions of the transistors are strained to produce an increase in the mobility of the charge carriers and thus an increase in the on-state current of the device (at a given drain potential).
One method that is currently used to induce channel strain is to grow a compressively strained SiGe layer in a recessed region adjacent to the channel region of the device, as described in U.S. Pat. No. 6,621,131, “Semiconductor Transistor Having a Stressed Channel,” issued Sep. 16, 2003. The SiGe layer then serves as the S/D of the device and imparts uniaxial strain on the channel. The amount of strain in the channel will be proportional to the stress applied by the SiGe layer, which would typically increase with the Ge content of the SiGe. Since increased strain in the channel correlates with better device performance, there is a great interest in SiGe stressors having a high Ge content.
One of the primary challenges in using single-crystal strained regions as a stressor for the channel is to prevent the formation of strain relieving dislocations during strained region growth and subsequent processing. It has been found that the ion implantation step that is used to dope and electrically activate the S/D regions facilitates the relaxation of the strain in the SiGe S/D regions, as illustrated in FIGS. 2A-2F, which show, in cross section view, the steps in fabricating a FET with channel strain induced by embedded SiGe S/D regions whose processing requires at least one ion implantation step.
FIG. 2A shows SOI FET 200 at an early stage of processing. SOI FET 200 comprises single crystal SOI layer 210 disposed on buried oxide (box) layer 220 on base substrate 230, with conductive gate 240 disposed on gate dielectric 250 over SOI channel region 260 separating SOI S/D regions 270. FIG. 2B shows the structure of FIG. 2A after S/D regions 270 have been etched away to form cavities 280. Cavities 280 are then replaced by epitaxially grown SiGe stressor S/D regions 290 which exert a force on the channel region, as indicated by arrows 300 in FIG. 2C. Implantation of SiGe regions 290 by non-amorphizing implant 310 produces multiple defects 320 as shown in FIG. 2D. These defects act as nucleation sites for strain-relieving dislocations 330 that form during subsequent activation annealing, as shown in FIG. 2E, where short arrows 340 indicate the reduced force of the S/D regions on channel region 260 as compared to longer arrows 300 in FIG. 2C.
Certain implantation conditions (particularly those involving heavy ions such as As+) can result in a significant and irreversible reduction in strain after a prescribed thermal treatment step called an “activation anneal.” Since the driving force for strain relaxation increases with strain, SiGe alloys with a high Ge content are particularly susceptible to undesired relaxation. A method for S/D ion implantation and activation that minimizes S/D plastic relaxation and preserves as much strain as possible would be highly desirable.
The efficacy of heated implants in reducing ion implant damage in bulk semiconductors has been known for some time. The threshold dose of implanted ions required to amorphize a given semiconductor region in a substrate increases with substrate temperature because the transition from a crystalline material to an amorphous one is determined by the competition between the temperature-independent rate at which the damage and disorder are generated by the implanted ions and the temperature-dependent rate at which the implant damage can be spontaneously repaired. For example, the threshold dose required for amorphization with 200 keV B implanted at low current densities into 100-oriented single crystal Si increases by a factor of 40 as the Si substrate temperature is increased from 200 K to 300 K as described by F. F. Morehead et al., J. Appl. Phys. 43 1112 (1972). While these and similar effects are well known for bulk Si and the III-Vs, the benefits of hot implants have not been previously applied to solve the new problems addressed by the present invention, namely, reduction and/or elimination of (i) implant-induced source/drain amorphization in UTSOI CMOS, and (ii) implant-induced plastic relaxation in FETs with strained source/drain regions.
It is therefore an object of this invention to provide an ion implantation method that allows the desired dopant density profiles to be achieved with satisfactorily limited amorphized layer thicknesses and/or satisfactorily low levels of strain relaxation.
It is a further object of this invention to provide an alternative to the ion implantation method above, wherein said alternative also produces satisfactorily limited amorphized layer thicknesses and/or satisfactorily low levels of strain relief, that is easier to implement with existing tooling.